Extracted text: 3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description: (a) module Circuit_A (A, B, C, D, F); input output A, B, C. D: F; w, x, y, z, a, d; (x, B, C, d); (v, a .C): wire or and (y, a ,C); (w. z B): and and (z, y, A); (F, x, w); (a, A); (d, D); endmodule or not not (b) module Circuit_B (F1, F2, F3, A0, A1, BO, B1); F1, F2, F3; output input A0, A1, B0, B1; (F1, F2, F3); (F2, w1, w2, w3); (F3, w4, w5): (PS, W4, (w1, w6, B1); nor or and and (w2, w6, w7, B0); (w3, w7, B0, B1); or and (w6, A1); (w7, A0): not not (w4, A1, B1); (w5, A0, BO); xor xnor endmodule (c) module Circuit_C (y1, y2, y3, a, b); output y1, y2, y3; input a, b; assign y1 = a || b; and (y2, a, b); assign y3 = a && b: endmodule