Extracted text: 3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description: (a) module Circuit_A (A, B, C, D, F); input output wire A, B, C, D; F; w, X, y, z, a, d; (x, B, C, d); (y, a ,C); (w, z ,B); (z, y, A); (F, x, w); (а, А); (d, D); or and and and or not not endmodule