Extracted text: 3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description: (а) *A (A. B. CD F; and nodu (b) module Circuit_B (F1, F2, F3, A0, A1, B0, B1); output input F1, F2, F3; A0, A1, B0, B1; (F1, F2, F3); (F2, w1, w2, w3); (F3, w4, w5); (w1, w6, B1); (w2, w6, w7, B0); (w3, w7, B0, B1); (w6, A1); (w7, A0); (w4, A1, B1); (w5, A0, BO); nor or and and or and not not xor xnor endmodule