[30] One possible implementation of the load linked/store conditional pair
for multi core processors is to constrain these instructions to using un cached memory
operations. A monitor unit intercepts all reads and writes from any core to the
memory. It keeps track of the source of the load linked instructions and whether
any intervening stores occur between the load linked and its corresponding store
conditional instruction. The monitor can prevent any failing store conditional from
writing any data and can use the interconnect signals to inform the processor that
this store failed.
Design such a monitor for a memory system supporting a four-core SMP. Take
into account that, generally, read and write requests can have different data sizes (4/
8/16/32 bytes). Any memory location can be the target of a load linked/store conditional pair, and the memory monitor should assume that load linked/store
conditional references to any location can, possibly, be interleaved with regular
accesses to the same location. The monitor complexity should be independent
of the memory size.