4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use IN0_1, IN0_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the...

4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use IN0_1, IN0_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the outputs. Obtain the schematic diagram for a possible implementation of such a mux following the example given in Figure 3.3 correctly.

Extracted text: 3 M 3 OUT K 3 Figure 3.3: A word-sized two input AND gate.