3) Assume that there is a cache with 4 blocks and the block size is 1 byte (in total only 4B cache). The cache is initially empty. For two different configurations of the cache; direct-mapped and...

3) Assume that there is a cache with 4 blocks and the block size is 1 byte (in total only 4B cache). The cache is initially empty. For two different configurations of the cache; direct-mapped and 2-way set associative, given memory addresses are accessed in the given order. Write if given addresses are hit or miss in the cache.

address: 3 - 11 - 0 - 3 - 11