2. We examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX МЕМ WB 200 ps...

Extracted text: 2. We examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX МЕМ WB 200 ps 300 ps 150 ps 250 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: alu (i.e. add, sub,...) beq Iw sw 45 % 20 % 20 % 15% a. What is the clock cycle time in a pipelined and non-pipelined processor?