1,1II 1,11,1II 1,1II,IV II,IV timescale Ins / lps module mainfunction (input a,b,c, output y); assign y=(a&b) |(a|c); endmodule timescale lns / lps module testbench; reg a,b,c; mainfunction dt (.a...

Extracted text: 1,1II 1,11,1II 1,1II,IV II,IV timescale Ins / lps module mainfunction (input a,b,c, output y); assign y=(a&b) |(a|c); endmodule timescale lns / lps module testbench; reg a,b,c; mainfunction dt (.a (a),.b (b),.c(c),.y(y)); initial begin a=0; b=0; c=0; #10 if(y!==1) $display("y=logic 0"); end endmodule Which of the following is true for the two verilog codes above? I. Behavioral design level is used. II. Output(y) is equal to logic 1 and the text "y=logic 0" appears in the simulation. III. The combinational circuit designed in the code includes 3 logic gates. IV. A net has to be added to the code for the output.