[10/10/10/10/10/10/10] For each part of this exercise, the initial cache and memory state are assumed to initially have the contents shown in Figure 5.37. Each part of this exercise specifies a...

[10/10/10/10/10/10/10] For each part of this exercise, the initial cache and memory state are assumed to initially have the contents shown in Figure 5.37. Each part of this exercise specifies a sequence of one or more CPU operations of the form Ccore#: R, for reads and Ccore#: W, for writes. For example, C3: R, AC10 & C0: W, AC18 Read and write operations are for 1 byte at a time. Show the resulting state (i.e., coherence state, tags, and data) of the caches andmemory after the actions given below. Show only the cache lines that experience some state change; for example: C0.L0: (I, AC20, 0001) indicates that line 0 in core 0 assumes an “invalid” coherence state (I), stores AC20 from the memory, and has data contents 0001. Furthermore, represent any changes to the memory state as M: