1. Suppose the memory cells at addresses 00 through 03 in the machine described in Appendix C contain the following bit patterns: (Asterisked problems are associated with optional sections.) Chapter...

1.
Suppose the memory cells at addresses 00 through 03 in the machine described in Appendix C contain the following bit patterns: (Asterisked problems are associated with optional sections.)Chapter Review Problems

Address Contents

00 22

01 11

02 32

03 02

04 C0

05 00

Assuming that the program counter initially contained 00, record the contents of the program counter, instruction register, and memory cell at address 02 at the end of each fetch phase of the machine cycle until the machine halts.