1. Design a sequence detector circuit in verilog. The circuit is supposed to have a one-bit digital input. When you provide the last two digits of your student ID to the input (starting from least...

Extracted text: 1. Design a sequence detector circuit in verilog. The circuit is supposed to have a one-bit digital input. When you provide the last two digits of your student ID to the input (starting from least significant) the output of the circuit will go high. 2. Draw the state diagram. 3. Write the verilog code. 4. a. Draw the circuit block diagram showing the state memory and next state and output logic blocks (similar to the figure provided below). b. Inside each block write the corresponding verilog code. c. Mark the verilog signal name on each bus arrow.


Extracted text: inputs : Next-state excitation Logic Output Logic State current state Memory outputs F G clock input clock signal