1. An FSM has an input w and an output z. The machine has to generate z = 1 when the following patterns in w are detected: 11 or 111; otherwise, z = 0. Reset functionality is not mandatory. Draw the...

Solve in Python

Extracted text: 1. An FSM has an input w and an output z. The machine has to generate z = 1 when the following patterns in w are detected: 11 or 111; otherwise, z = 0. Reset functionality is not mandatory. Draw the state diagram, the state- assigned table, write the Verilog code, run simulations and verify your answer. An example timing diagram can be found here: clock t. t t t. ts t. t t. t tio tn tr2 111010 1 1 1 1 00 1 1 0 1 1 1 Expected Output: The timing diagram should contain waveforms as described in the table. The clock period should be 10 ns. The discussion must contain a state diagram, state assigned table, and brief explanations of all high output situations e.g. z is high during ts, t11, and t12 clock cycles. Briefly explain these situations in light of the problem statement and your derived state diagram/state assigned table.